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100%: Pascal Meinerzhagen; Adam Teman; Robert Giterman; Noa Edri; Andreas Burg; Alexander Fish: / / | Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip | Springer | Softcover reprint of the original 1st ed. 2 (ISBN: 9783319868554) 2018, Springer Nature, in Englisch.Nur diese Ausgabe anzeigen…
61%: Adam Teman, Alexander Fish, Andreas Burg, Noa Edri, Pascal Meinerzhagen, Robert Giterman: Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip als eBook Download von And. (ISBN: 9783319604022) 2017, in Deutsch, auch als eBook.Nur diese Ausgabe anzeigen…
/ / | Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip | Springer | Softcover reprint of the original 1st ed. 2
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Bester Preis: Fr. 6.27 (€ 6.41)¹ (vom 05.09.2019)1
Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip
~EN PB NWISBN: 9783319868554 bzw. 3319868551, vermutlich in Englisch, Springer Shop, Taschenbuch, neu.
Lieferung aus: Deutschland, Lagernd.
This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy. Soft cover.
This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy. Soft cover.
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/ Teman / Giterman | Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip | Springer | Softcover reprint of the original 1st ed. 2
DE PB NWISBN: 9783319868554 bzw. 3319868551, in Deutsch, Springer, Taschenbuch, neu.
This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.
4
Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip als eBook Download von And.
DE NW EBISBN: 9783319604022 bzw. 3319604023, in Deutsch, Springer-Verlag GmbH, neu, E-Book.
Die Beschreibung dieses Angebotes ist von geringer Qualität oder in einer Fremdsprache. Trotzdem anzeigen
5
Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip
DE NW EB DLISBN: 9783319604022 bzw. 3319604023, in Deutsch, Springer-Verlag, neu, E-Book, elektronischer Download.
Lieferung aus: Deutschland, E-Book zum Download.
Die Beschreibung dieses Angebotes ist von geringer Qualität oder in einer Fremdsprache. Trotzdem anzeigen
Die Beschreibung dieses Angebotes ist von geringer Qualität oder in einer Fremdsprache. Trotzdem anzeigen
6
Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip (2018)
~EN HC NW RPISBN: 9783319868554 bzw. 3319868551, vermutlich in Englisch, gebundenes Buch, neu, Nachdruck.
Lieferung aus: Deutschland, Next Day, Versandkostenfrei.
Die Beschreibung dieses Angebotes ist von geringer Qualität oder in einer Fremdsprache. Trotzdem anzeigen
Die Beschreibung dieses Angebotes ist von geringer Qualität oder in einer Fremdsprache. Trotzdem anzeigen
7
Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip
DE NWISBN: 9783319604022 bzw. 3319604023, in Deutsch, Springer International Publishing, neu.
Lieferung aus: Deutschland, Versandkostenfrei.
Die Beschreibung dieses Angebotes ist von geringer Qualität oder in einer Fremdsprache. Trotzdem anzeigen
Die Beschreibung dieses Angebotes ist von geringer Qualität oder in einer Fremdsprache. Trotzdem anzeigen
8
Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip (2017)
DE NW EB DLISBN: 9783319604022 bzw. 3319604023, in Deutsch, Springer, Springer, Springer, neu, E-Book, elektronischer Download.
Lieferung aus: Deutschland, in-stock.
Die Beschreibung dieses Angebotes ist von geringer Qualität oder in einer Fremdsprache. Trotzdem anzeigen
Die Beschreibung dieses Angebotes ist von geringer Qualität oder in einer Fremdsprache. Trotzdem anzeigen
9
Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip
DE NWISBN: 9783319868554 bzw. 3319868551, in Deutsch, Springer Nature, neu.
Lieferung aus: Vereinigtes Königreich Grossbritannien und Nordirland, Lagernd.
Die Beschreibung dieses Angebotes ist von geringer Qualität oder in einer Fremdsprache. Trotzdem anzeigen
Die Beschreibung dieses Angebotes ist von geringer Qualität oder in einer Fremdsprache. Trotzdem anzeigen
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